Aįrom the above truth table of 3 lines to 8 line decoder, the logic expression can be defined asįrom the above Boolean expressions, the implementation of 3 to 8 decoder circuit can be done with the help of three NOT gates & 8-three input AND gates. From the following truth table, we can observe that simply one of 8 outputs from DO – D7 can be selected depending on 3 select inputs. So, the truth table of this 3 line to 8 line decoder is shown below. The selection of 8 outputs can be done based on the three inputs. Here the inputs are represented through A, B & C whereas the outputs are represented through D0, D1, D2…D7. In 3 to 8 line decoder, it includes three inputs and eight outputs. 3 Line to 8 Line Decoder using Logic Gates So, these outputs are the higher 8 minterms. In the above decoder, the A3 input is connected to enable the pin to obtain the outputs from Y15 – Y8. Here the compliment of A3 is given to enable the pin of the decoder to obtain the outputs like Y7 to Y0. The parallel inputs like A2, A1 & A0 are given to 3 lines to 8 line decoder. Here, the block diagram is shown below by using two 2 to 4 decoders. So, for implementing a single 3 to 8 decoder, we need two 2 lines to 4 line decoders. The number of o/ps for higher-order decoder is ‘m2’įor instance, when m1 = 4 & m2 = 8, then substitute these values in the above equation. The number of o/ps for the lower-order decoder is ‘m1’ The number of lower-order decoders required is m2/m1 The following formula is used to implementation of higher-order decoders with the help of low order decoders So, in 3 lines to 8 line decoder, it includes three inputs like A2, A1 & A0 and 8 outputs from Y7 – Y0. We have discussed above that 2 to 4 line decoder includes two inputs and four outputs. The implementation of this 3 line to 8 line decoder can be done using two 2 lines to 4 line decoders. Logic Diagram of 2 to 4 Decoder 3 Line to 8 Line Decoder Implementation Likewise, 3 line to 8 line decoder generates eight minterms for 3 input variables of A0, A1 & A2. If enable is zero, afterward all the decoder’s outputs will be equivalent to zero. Thus, this decoder’s output is nothing but the minterms of inputs and enable is equivalent to 1. The 2 to 4 decoder logic diagram is shown below. So the four product terms can be implemented through 4 AND gates where each gate includes 3 inputs as well as 2 inverters. The boolean expression for every output isĮvery output of this decoder includes one product term.
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